This invention relates in general to techniques and circuitry for providing controlled access by one processor at a time of two or more processors, to a system resource shared by the two or more processors and in particular, to a time multiplexing technique and corresponding circuitry to provide such access.
Conventionally, arbiter circuitry is interposed between a system resource and two or more processors sharing access to that resource. If two or more processors request access to the resource at the same time, the arbiter circuitry determines which of the two or more processors is to be allowed access by a first-in-time and/or priority scheme. This prevents two or more processors from simultaneously accessing and/or modifying the contents of the shared resource and as a consequence, one processor contaminating the contents of the resource for the other processors.
Inclusion of arbiter circuitry in an integrated circuit chip, however, increases the size and complexity of the chip and as a result, can increase its cost and reduce its performance. Further, additional protocol handling requirements on the access requesting processors is required in order to interface with the arbiter circuitry and as a result, can interfere with the execution of other important activities being conducted by these processors.